Mechanical Engineer

• Micro architect and RTL Design of SoC SubSystem/IP blocks
• Will develop UPF and run CLP checks
• Will be responsible for RTL quality checks - Lint/CDC/LEC
• Create appropriate documentation for hardware blocks
• Responsible for analyse / debug / fixing issues reported by verification team
• Will develop the synthesis constraints for the blocks / subsystem
• Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation

Staff/Sr Staff RTL Design Engineer

Mechanical Engineer