Staff/Sr Staff RTL Design Engineer
Alphawave Semi
full-time
Posted on:
Location Type: Remote
Location: Remote • 🇨🇦 Canada
Visit company websiteJob Level
Senior
About the role
- Micro architect and RTL Design of SoC SubSystem/IP blocks
- Will develop UPF and run CLP checks
- Will be responsible for RTL quality checks - Lint/CDC/LEC
- Create appropriate documentation for hardware blocks
- Responsible for analyse / debug / fixing issues reported by verification team
- Will develop the synthesis constraints for the blocks / subsystem
- Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation
Requirements
- Strong background with multi-year and multi-project experience in RTL SoC Design (Verilog/VHDL), and ASIC/FPGA debug methodologies
- Experience in SerDes PHY, DSP, and Analog mixed signal is desirable
- Knowledge in Ethernet and PCIe standards is desirable
- Proficient in reviewing high-level test plans and coverage metrics.
- Expertise in Design Compiler Synthesis and formal verification using LEC.
- Comprehensive understanding of timing closure.
- Experience in post-silicon bring-up and debugging.
- Team player with strong communication skills to ensure effective program execution.
Benefits
- Health & Wellness programs that emphasize knowledge and prevention, helping you stay proactive and prepared to manage your health at every stage.
- Comprehensive health plans
- Wellness Spending Account (WSA)
- Employee Assistance Program (EAP)
- Paid Vacation
- Paid Holidays
- Parental Leave
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
RTL DesignVerilogVHDLASICFPGADesign Compiler Synthesisformal verificationtiming closureSerDes PHYDSP
Soft skills
communication skillsteam player