Hardware Engineer

• Develop and support Ambiq’s embedded AI runtimes (HeliaRT—our fork/extension of TensorFlow Lite for Microcontrollers—and HeliaAOT) with focus on portability, correctness, performance, and usability.
• Implement and optimize ML operator kernels and embedded libraries for on-chip acceleration (DSP, vector, NPU), including HeliaDSP and HeliaCore components.
• Build and maintain on-device profiling and performance analysis tools, including converting PMU counters into actionable insights.
• Drive improvements in latency, memory footprint, and energy (e.g., joules/inference) through compute/bandwidth and memory-hierarchy analysis.
• Develop benchmark harnesses, microbenchmarks, and regression tests to ensure numerical correctness and prevent performance regressions.
• Enable seamless customer integration across embedded environments and toolchains (bare metal, FreeRTOS, Zephyr).
• Improve memory planning/runtime efficiency and manage upstream/fork health; publish and maintain customer-facing assets (docs, guides, examples, benchmarks).

Principal Edge AI Firmware Engineer

• Taking an end-to-end responsibility for software you develop, including: Designing, analyzing, implementing, testing, deploying, documenting and performing ongoing maintenance.
• Contributing to and integrating with programs developed by others.
• Preparing and presenting content on new technologies and learnings as part of internal community education efforts.
• Participating & filing for intellectual property.

Principal Firmware Engineer

• Define and execute the long-term hardware vision and strategy for our video surveillance products, aligning with overall business objectives.
• Lead and mentor a large, multidisciplinary team of hardware engineers, including electrical, mechanical, and test engineers.
• Drive the design, development, and delivery of innovative, high-quality, and reliable video surveillance camera hardware.
• Foster an environment of continuous improvement and innovation, encouraging the team to explore new technologies and challenge the status quo.
• Partner closely with software engineering, product management, and other cross-functional teams and stakeholders to influence strategic priorities, ensure seamless integration, and a cohesive product strategy.
• Provide technical guidance and oversight throughout the product lifecycle, from concept and prototyping to production and post-launch support.
• Implement and refine engineering processes to enhance and improve efficiency, scalability, stability, quality, and security of our products and services.

Director of Hardware Engineering – Video Devices

• lead system-level architecture planning for Server/AI platforms, including product configuration definition, functional partitioning, and mechanical/thermal/power/cooling feasibility alignment
• drive the definition of system requirements, interface specifications, and early configuration options (e.g., GPU, accelerator, storage, and compute servers)
• conduct architectural trade-off analysis balancing performance, cost, power, scalability, and manufacturability
• collaborate with EE, thermal, mechanical, BMC, and firmware architects to form a complete product-level concept package
• work with Architecture and BU teams to evaluate RFQ/RFI requirements and generate competitive architecture proposals
• define and propose system topologies, mechanical footprints, airflow design, I/O mappings, and cabling options
• interface with customers and internal stakeholders to align design intent and value proposition during the concept phase
• present and document concept proposals that include block diagrams, design strategy, trade-off summary, and risk evaluation
• stay up to date with Open Compute (OCP), Computer Express Link (CXL) or Open BMC
• evaluate and integrate technology enablers such as PCIe Gen5/6, high-efficiency power stages, and new materials
• participate in roadmap planning with BU/CTO to ensure platform reusability and alignment with future-generation technologies
• define how electrical, mechanical, thermal, and firmware domains interact to support functional and performance goals
• coordinate platform-level integration strategies including MB placement, airflow optimization, and system serviceability
• align system-level DFM/EMC/thermal reliability requirements in early phase and guide downstream teams with clear targets
• lead the creation of architecture decks, system requirements, platform-level block diagrams, and BoM-level feasibility plans
• drive internal and customer-facing design reviews for architecture alignment and requirement sign-off
• maintain issue-tracking and lessons-learned documentation to improve future concept efficiency

Hardware Engineering Architect, Server

• Lead development of DFT solutions for next-generation ASICs for multi-100G to 1.6T coherent optical communications products
• Lead implementation of SSN, hierarchical test flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, using Siemens Tessent, or Synopsys, tools for RTL and gate netlist DFT implementation
• Generate and deliver ATPG test pattern for stuck-at, transition, cell aware and path delay fault models
• Drive scan-based diagnosis methodology for Silicon failure debug
• Provide post-silicon testing and validation support
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
• Perform simulation runs and debug for non-timing and back annotated timing (SDF) gate level simulations
• Develop test scripts, automate processes, and analyze data using programming languages such as Python, Tcl, or C++

ASIC Engineering Technical Lead – DFT

• Provide technical coordination and program leadership for end‑to‑end execution of Slingshot switch and NIC ASIC programs
• Develop and drive integrated execution plans, including schedules and critical deliverables
• Track execution progress, risks, dependencies, and mitigation or recovery plans
• Serve as a primary interface between silicon engineering and other teams
• Communicate program status, issues, risks, and escalation plans to senior leadership
• Manage internal and external development partners
• Drive alignment between business demand and design quality
• Lead execution through manufacturing milestones
• Provide guidance and mentoring to less‑experienced program managers and engineers

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Principal Edge AI Firmware Engineer

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