Digital Integrated Circuit Design Verification Engineer
Snap Inc.
full-time
Posted on:
Location Type: Remote
Location: Washington • United States
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Salary
💰 $173,000 - $259,000 per year
About the role
- Work as part of a multi-disciplinary team designing display Integrated Circuits for AR
- Work closely with digital design, analog logic, software and verification engineers
- Develop and implement UVM-based and assertion-based testbenches
- Create and execute verification test plans, including functional coverage and code coverage
- Utilize Siemens Questa tool set for verification and debug tasks
- Specify and configure tools and create automation
Requirements
- BSEE or MSEE or relevant years of experience
- 10+ years of experience in ASIC Design Verification
- Strong knowledge of UVM and SystemVerilog for advanced verification methodologies
- Strong knowledge of digital functional simulation, and tools such as Siemens Questa
- Strong knowledge of good Verilog RTL coding practices
- Scripting and automation, such as TCL, Make, Perl, Python and Shell scripts in Linux environment
Benefits
- paid parental leave
- comprehensive medical coverage
- emotional and mental health support programs
- compensation packages that let you share in Snap’s long-term success
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
ASIC Design VerificationUVMSystemVerilogVerilog RTL coding practicesdigital functional simulationTCLMakePerlPythonShell scripts
Certifications
BSEEMSEE