Senior Digital Verification Engineer

NXP Semiconductors

Digital Verification Engineer verifying secure digital hardware architectures and co-processors at NXP Semiconductors. Developing SystemVerilog/UVM environments, closing coverage gaps, and supporting security IP across product lifecycles.

Posted 8/4/2026full-timeGlasgow • 🇬🇧 United KingdomSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in SystemVerilog and UVM for developing and verifying complex digital hardware architectures, while effectively mentoring team members and driving technical excellence throughout the product lifecycle.

Highest-signal resume keywords

SystemVerilog Testbench DevelopmentUVM Component CreationConstrained Random Verification TechniquesMetrics-Driven VerificationSystemVerilog Assertions

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SystemVerilogUVMConstrained Random VerificationMetrics-Driven VerificationSystemVerilog AssertionsCoverage ClosureDebugging SkillsFormal Verification Methods

Soft Skills

MentoringTechnical ExcellenceCollaboration

Certifications & Qualifications

BSc. or MSc. Degree in Electronics or Electrical Engineering

Industry Keywords

Digital Hardware ArchitecturesVerification PlansVerification StrategiesTest-Chip ValidationSilicon Validation

About the role

Key responsibilities & impact

Verify the functional behaviour of complex digital hardware architectures
Create, review, and maintain verification plans and track verification progress
Specify and develop verification strategies, tests, and environments for security features and hardware co-processors
Work with emerging verification methodologies and introduce them into existing verification flows
Mentor junior team members in best practices
Drive technical excellence and consistency across teams
Contribute across the full product lifecycle, from requirements capture and architectural definition through development and verification to test-chip and silicon validation

Requirements

What you’ll need

BSc. or MSc. degree in Electronics or Electrical Engineering
Strong hands-on experience with SystemVerilog for testbench development and verification
Proven expertise in UVM, including component creation, sequences, drivers, monitors, and scoreboards
Solid understanding and practical use of Constrained Random Verification techniques
Experience with Metrics-Driven Verification, including functional coverage and verification planning
Ability to write SystemVerilog Assertions (SVA) for protocol and design checking
Demonstrated success in achieving coverage closure across functional and code coverage metrics
Experience analysing coverage results and refining test strategies to close gaps
Strong debugging skills across simulations and complex verification environments
Knowledge of Formal Verification methods would be advantageous

Benefits

Comp & perks

Online and offline learning opportunities for career and professional skills development
Inclusive work environment
Diversity, inclusion and equality programs