Senior Principal Design Engineer

NXP Semiconductors

Senior Principal Design Engineer responsible for SoC u-Architecture and RTL Integration at NXP. Focusing on high design quality, mentorship, and collaboration with cross-functional teams.

Posted 6/30/2026full-timeBangalore • 🇮🇳 IndiaSeniorWebsite

About the role

Key responsibilities & impact

SoC u-Architecture for Clocking, Reset, Core & Interconnects
SoC RTL Integration using state-of-the-art tools, flows & methodologies
LINT/CDC/RDC signoffs for the highest design quality
Conducting IP Integration reviews, BE reports reviews for concurrent engineering
Driving key SoC design methodologies in collaboration with global cross functional teams
Overseeing technical documentation in close collaboration with information development team

Requirements

What you’ll need

Responsible for SoC u-Architecture for Clocking, Reset, Core & Interconnects, Power Management, Debug & Trace, Functional Safety, Security
Experience in SoC RTL Integration using state-of-the-art tools, flows & methodologies
Knowledge of LINT/CDC/RDC signoffs for highest design quality
Conducting Handoff checks including Verification smokesuite and express Synthesis
Familiarity with Requirements management and traceability including IS026262 / CMMi compliance
Experience overseeing technical documentation
Ability to mentor other engineers based on core competence and expertise

Benefits

Comp & perks

Career Development Opportunities
Online and offline learning opportunities

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

SoC U-ArchitectureSoC RTL IntegrationLINT SignoffCDC SignoffRDC SignoffPower ManagementDebug & TraceFunctional SafetySecurityVerification Smokesuite

Soft Skills

MentoringCollaboration

Certifications

ISO26262CMMI Compliance