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Principal DFT Engineer
NXP SemiconductorsDFT Engineer with expertise in Scan Insertion, ATPG, and GLS for complex SoCs. Collaborating across teams to ensure high fault coverage and timely tape-out support at NXP.
About the role
Key responsibilities & impact- Implementing and verifying scan architectures
- Performing scan insertion
- Generating and analyzing ATPG patterns for stuck-at and transition faults
- Executing GLS with and without SDF for DFT validation
- Collaborating with RTL, physical design, and test teams to ensure high fault coverage
- Ensuring clean DFT signoff and timely tape-out support
Requirements
What you’ll need- 7-12 years of experience in DFT Engineering
- Strong hands-on expertise in Scan Insertion, ATPG, and Gate-Level Simulation (GLS)
- Proficiency with industry-standard DFT tools (Mentor/Siemens Tessent, Synopsys, Cadence)
- Solid Verilog/SystemVerilog skills
- Ability to debug DFT and GLS issues independently
- Prior experience supporting pre- and post-silicon activities is a plus
Benefits
Comp & perks- Career Development Opportunities
- Commitment to sustainability
- Inclusive work environment
- Learning opportunities
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
Scan InsertionATPGGate-Level Simulation (GLS)VerilogSystemVerilog
Soft Skills
Independent DebuggingCollaboration