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Principal DFT Engineer
NXP SemiconductorsDFT Engineer with expertise in Scan Insertion, ATPG, and GLS for complex SoCs. Collaborating across teams to ensure high fault coverage and timely tape-out support at NXP.
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates extensive expertise in DFT Engineering, focusing on Scan Insertion, ATPG pattern generation, and Gate-Level Simulation (GLS) for effective fault coverage and validation. Proficient in collaborating with cross-functional teams to ensure successful DFT signoff and timely tape-out support.
Highest-signal resume keywords
DFT Engineering ExperienceScan Insertion ExpertiseATPG Pattern GenerationGate-Level Simulation (GLS)DFT Tools Proficiency
ATS Keywords
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Hard Skills
Scan InsertionATPGGate-Level Simulation (GLS)VerilogSystemVerilog
Soft Skills
Independent DebuggingCollaboration
Tools & Technologies
Mentor/Siemens TessentSynopsysCadence
Industry Keywords
DFT ValidationFault CoveragePre-Silicon ActivitiesPost-Silicon Activities
About the role
Key responsibilities & impact- Implementing and verifying scan architectures
- Performing scan insertion
- Generating and analyzing ATPG patterns for stuck-at and transition faults
- Executing GLS with and without SDF for DFT validation
- Collaborating with RTL, physical design, and test teams to ensure high fault coverage
- Ensuring clean DFT signoff and timely tape-out support
Requirements
What you’ll need- 7-12 years of experience in DFT Engineering
- Strong hands-on expertise in Scan Insertion, ATPG, and Gate-Level Simulation (GLS)
- Proficiency with industry-standard DFT tools (Mentor/Siemens Tessent, Synopsys, Cadence)
- Solid Verilog/SystemVerilog skills
- Ability to debug DFT and GLS issues independently
- Prior experience supporting pre- and post-silicon activities is a plus
Benefits
Comp & perks- Career Development Opportunities
- Commitment to sustainability
- Inclusive work environment
- Learning opportunities