NXP Semiconductors

Senior Analog Layout Engineer

NXP Semiconductors

full-time

Posted on:

Location Type: Office

Location: Kuala Lumpur • Malaysia

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Job Level

Senior

Tech Stack

DAC

About the role

  • Perform full‑custom analog layout for critical circuit blocks
  • Translate schematics into high‑quality, silicon‑proven layouts in advanced nodes
  • Apply best‑in‑class techniques for matching and symmetry, parasitic control, noise isolation
  • Run and debug DRC, LVS, ERC , EM/IR, and reliability checks
  • Work with designers to close LVS and performance issues
  • Support silicon bring‑up, debug, and yield improvement

Requirements

  • BSEE or equivalent in Electrical / Electronics Engineering (preferred)
  • 6–10 years of hands‑on experience in custom analog / mixed‑signal layout
  • Proven experience working in 28nm, 22nm, and/or 16nm CMOS process technologies
  • Demonstrated experience laying out complex analog IP blocks (AFE, ADC, DAC, PLL, regulators)
  • Strong proficiency with Cadence Virtuoso Layout Suite and Calibre (DRC, LVS, PEX)
  • Solid understanding of foundry design rules
Benefits
  • Career Development Opportunities
  • Commitment to diversity, inclusion and equality
  • Professional development
Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools
analog layoutcustom analog layoutmixed-signal layoutDRCLVSERCEM/IRreliability checkssilicon bring-upyield improvement
Certifications
BSEE