Senior SRAM Engineer

NVIDIA

Senior SRAM Engineer designing custom memory circuits for NVIDIA’s AI and processing chips. Optimizing circuit performance, area, power, layout, and silicon robustness.

Posted 8/24/2026full-timeRemote • California • 🇺🇸 United StatesSenior💰 $196,000 - $310,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in SRAM circuit design and optimization, with a strong focus on performance, area, and power efficiency. Proficient in design automation methodologies and collaboration with cross-functional teams to ensure high-quality silicon outcomes.

Highest-signal resume keywords

SRAM Circuit DesignMemory Design TechniquesCadence VirtuosoStatic Timing AnalysisVerilog Scripting

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Circuit DesignSRAM DesignMacro/Block DevelopmentData AnalysisDesign AutomationSPICE SimulationWaveform ViewingEM AnalysisIR AnalysisFormal Functional Verification

Soft Skills

Self-MotivationAttention to DetailClear Presentation Skills

Tools & Technologies

Cadence VirtuosoSPICE SimulatorsWaveform ViewersPerlPythonShell

Industry Keywords

Electrical EngineeringComputer EngineeringProcessor ArchitectureDesign MethodologiesHigh-Quality Layouts

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Design SRAM circuits using state-of-the-art technology processes
Optimize circuits for performance, area, and power
Collaborate with mask designers to create high-quality, dense pitch-matched layouts
Verify functionality, electrical integrity, and robustness
Improve and develop flows and methodologies for design automation, data collection, and analysis to ensure working silicon
Design specialized RAM implementations across NVIDIA's processing chips and collaborate with processor architecture teams

Requirements

What you’ll need

BS/MS/PhD (or equivalent experience) in Electrical or Computer Engineering
Minimum 12 years of circuit design experience
Strong understanding of SRAM and memory design techniques and macro/block development
Self-motivation, attention to detail, clear data analysis and presentation skills
Familiarity with Cadence Virtuoso for schematic and layout, SPICE simulators, and waveform viewers
Background developing and using Static Timing Analysis, EM and IR analysis, and Formal Functional Verification flows and methodologies
Experience with Perl, Python, Shell, and Verilog scripting languages

Benefits

Comp & perks

Equity
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