Custom SOC IP Verification Engineer

NVIDIA

Custom SoC/IP Verification Engineer validating NVIDIA’s fabric and interconnect designs. Building SystemVerilog/UVM verification environments for next-generation AI and accelerated-computing chips.

Posted 8/20/2026full-timeSanta Clara • California, Texas • 🇺🇸 United StatesMid-LevelSenior💰 $136,000 - $264,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC design verification, particularly for fabric and interconnect IP blocks, utilizing SystemVerilog and UVM methodologies. Proficient in developing test plans and testbenches while collaborating across multiple engineering teams to ensure compliance and performance of interconnect subsystems.

Highest-signal resume keywords

ASIC VerificationSystemVerilogUVM MethodologyInterconnect ProtocolsPerformance Verification

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC Design VerificationSystemVerilog TestbenchesUVM-Based Test PlansConstrained-Random TestingScripting LanguagesPerformance VerificationBandwidth AnalysisLatency AnalysisFormal VerificationAssertion-Based Verification

Soft Skills

CollaborationProblem-Solving

Tools & Technologies

PalladiumVeloce

Industry Keywords

Fabric VerificationInterconnect VerificationNetwork-On-ChipSoC ArchitecturesBus Protocols

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Perform ASIC design verification of fabric and interconnect IP blocks and full chip integration, covering DMA, routing, arbitration, ordering, flow control, and protocol compliance
Develop and implement UVM-based test plans for fabric and interconnect verification at IP and system levels
Design and implement constrained-random and directed SystemVerilog testbenches for interconnect fabrics, NoC topologies, and multi-agent SoC integrations
Collaborate with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams
Drive silicon and platform verification strategies and methodologies for fabric and interconnect subsystems
Verify correctness, performance, and compliance of on-chip fabrics and interconnect subsystems from IP bring-up through full-chip integration

Requirements

What you’ll need

B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience)
5+ years of experience in ASIC verification, with a strong focus on fabric, interconnect, or network-on-chip verification at both IP and full chip levels
Strong knowledge of SystemVerilog and UVM methodology
Hands-on experience with industry-standard interconnect and bus protocols (e.g., AMBA AXI, CHI, or equivalent), with solid understanding of ordering, coherency, and flow control semantics
Familiarity with SoC architectures, NoC topologies, and multi-initiator/multi-target interconnect designs
Proficiency in scripting languages (Python, Perl, TCL)
Knowledge of performance verification and bandwidth/latency analysis for interconnect fabrics
Exposure to verification IPs for bus protocols, or emulation platforms (e.g., Palladium, Veloce) for full chip fabric validation
Experience in GPU or AI accelerator SoC interconnect verification is desirable
Experience with formal verification or assertion-based verification (SVA) applied to fabric and protocol properties

Benefits

Comp & perks

Highly competitive salaries
Comprehensive benefits package
Equity
Benefits for you and your family