Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

NVIDIA

ASIC physical design engineer optimizing NVIDIA CPU interconnect networks and last-level caches. Driving synthesis, timing closure, and power-performance goals for accelerated computing products.

Posted 8/11/2026full-timeSanta Clara • California, Oregon • 🇺🇸 United StatesSenior💰 $136,000 - $264,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in physical design of CPU on-chip interconnect networks and last-level caches, with a strong focus on timing analysis, synthesis, and high-performance semiconductor designs. Proficient in collaborating with cross-functional teams to achieve performance, area, and power goals.

Highest-signal resume keywords

Master’s Degree In Electrical Engineering5+ Years Experience In High-Performance Semiconductor DesignsPhysical Design Expertise In High-Frequency DesignVerilog ExpertiseIn-Depth Knowledge Of ASIC Design Flow

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Physical DesignTiming AnalysisSynthesisFloor-PlanningMicro-Architecture DefinitionPerformance OptimizationArea OptimizationPower Goals AchievementRTL DesignVerification

Soft Skills

Strong Communication SkillsInterpersonal SkillsTeam Collaboration

Tools & Technologies

Industry-Standard Physical Design Tools

Industry Keywords

CPU DesignInterconnect DesignCache DesignASIC DesignHigh-Frequency Design

About the role

Key responsibilities & impact

Perform physical design of CPU on-chip interconnect networks and last-level caches
Execute implementation, synthesis, timing closure, and timing analysis
Collaborate with the logic design team on micro-architecture definition and feasibility
Achieve timing, area, performance, and power goals
Evaluate physical design for next-generation NVIDIA coherent interconnects and system-level caches
Work with the global CPU team on high-performance semiconductor designs

Requirements

What you’ll need

Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience
5+ years of experience in processor or related high-performance semiconductor designs
Physical design expertise in high-frequency design
Hands-on synthesis experience
Experience with timing analysis and floor-planning
In-depth knowledge of industry-standard physical design tools
Strongly desirable experience in interconnect, cache, or core design
Verilog expertise preferred
Deep understanding of ASIC design flow, including RTL design and verification, DFT, and ECO
Strong communication and interpersonal skills
Ability to work in a dynamic, global team

Benefits

Comp & perks

Equity
Benefits
Inclusive work environment
Equal opportunity employer