Senior Verification Engineer – ARM Fabric Unit Level

NVIDIA

Senior Verification Engineer developing UVM/SystemVerilog testbenches for NVIDIA’s ARM-based automotive fabric. Verifying complex units, subsystems, and SoCs across advanced Tegra chip technologies.

Posted 8/5/2026full-timeHyderabad • 🇮🇳 IndiaSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in UVM-based verification methodologies and ARM architecture, with a strong focus on developing efficient testbenches and ensuring verification closure for complex automotive systems. Collaborates effectively with cross-functional teams to enhance unit robustness and implement functional coverage.

Highest-signal resume keywords

UVM-Based VerificationSystemVerilogARM ArchitectureVerification ClosureAXI Protocol

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Applicant Tracking System Keywords

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Hard Skills

UVM-Based VerificationSystemVerilogVerification ClosureARM ArchitectureAXI ProtocolAHB ProtocolAPB ProtocolDebugging SkillsFunctional CoverageTest Plans

Soft Skills

Analytical SkillsCollaborationTeamwork

Tools & Technologies

Verification ToolsSimulation ToolsAI Tools

Industry Keywords

Automotive ChipsUnit-Level VerificationPost-Silicon VerificationBus Functional ModelsMatrix Organization

About the role

Key responsibilities & impact

Own HSIO IP unit-level verification for automotive chips and systems
Develop UVM-based verification test benches and methodologies
Verify in-house ARM architecture-based distributed fabric for transporting control, sidebands, and data
Architect testbenches and craft verification environments using SystemVerilog and UVM
Define test plans, tests, and verification infrastructure for modules, clusters, and systems
Build efficient and reusable bus functional models, monitors, checkers, and scoreboards
Implement functional coverage and coordinate verification closure for the unit
Collaborate with architects, designers, FPGA, and post-silicon teams to ensure unit robustness

Requirements

What you’ll need

BTech or MTech in ECE, EE, CSE, or an equivalent degree is required
4+ years of demonstrated ability in verification closure of complex units, sub-systems, or SOC-level verification
Proven experience in ARM architecture and AXI, AHB, and APB protocols
Experience with SystemVerilog and UVM verification methodologies
Good debugging and analytical skills
Exposure to industry-standard verification tools for simulation and debug
Ability to work as a diligent teammate and collaborate with cross-cultural global teams in a matrix organization
Exposure to AI tools such as Claude or Cursor for code development is a plus
Exposure to formal verification is advantageous

Benefits

Comp & perks

Highly competitive salaries
Comprehensive benefits package
Benefits for employees and their families
Reasonable accommodation for individuals with disabilities
Equal opportunity employment and diversity commitment