Senior ASIC Design Engineer – Clocks IP

NVIDIA

Senior ASIC Design Engineer responsible for clock design in GPU and CPU architectures. Collaborating with teams to enhance NVIDIA's innovative chip performance requirements.

Posted 8/3/2026full-timeSanta Clara • California, Texas • 🇺🇸 United StatesSenior💰 $136,000 - $264,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in ASIC execution and clock domain architecture, with a strong focus on Power, Performance, and Area (PPA) optimization. Proficient in RTL design and verification, with the ability to collaborate effectively across multiple teams.

Highest-signal resume keywords

RTL Design (Verilog)Power, Performance, and Area (PPA) OptimizationLogic Optimization TechniquesPython ScriptingClocking Network Implementation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DesignVerilogLogic SynthesisPower, Performance, and Area (PPA) OptimizationLogic Optimization TechniquesPythonScripting LanguagesClock Domain ArchitectureASIC ExecutionClocking Networks

Soft Skills

Interpersonal SkillsCollaboration

Certifications & Qualifications

BS in Electrical EngineeringMS in Electrical Engineering (Preferred)

Industry Keywords

GPUCPUSOCSub-Micron Silicon IssuesNoiseCross-TalkOCV Effects

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Architecting the clock domain to satisfy functional, physical and testing design requirements
Engage with multiple teams and design the GPU or CPU clocks
Improve Power, Performance, and Area (PPA) of NVIDIA chips
Collaborate with Physical design and timing team to evaluate Clocking concerns
Deliver clock RTL information to GPU, CPU and SOC verification team
Get involved in end-to-end cycle of ASIC execution

Requirements

What you’ll need

BS in Electrical Engineering or equivalent experience (MS preferred)
3+ years of relevant work experience
Deep understanding of logic optimization techniques and PPA trade-offs
Excellent interpersonal skills and ability to collaborate with multiple teams
Experience in RTL design (Verilog), verification and logic synthesis
Strong coding skills in python or other industry-standard scripting languages
Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus
Implementing on-chip clocking networks is a bonus

Benefits

Comp & perks

Competitive salaries
Generous benefits package
Equity options