Distinguished Engineer – End-to-End Scaling Performance Architecture

NVIDIA

Distinguished Engineer at NVIDIA defining application scaling strategies across multi-die, multi-GPU, and multi-node platforms. Leading architectural direction and driving performance improvements in accelerated computing.

Posted 7/29/2026full-timeSanta Clara • California, Texas, Washington • 🇺🇸 United StatesSeniorLead💰 $320,000 - $488,750 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in defining multi-generation strategies for application scaling, with a strong focus on system performance, workload characterization, and architectural trade-offs. Proven ability to influence cross-functional teams and mentor engineers in high-performance computing environments.

Highest-signal resume keywords

Multi-Generation Strategy DevelopmentSystem Performance AnalysisWorkload CharacterizationArchitectural Trade-Off EvaluationMentoring and Leadership

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DRAM Behavior AnalysisNVLink CommunicationC2C CommunicationPerformance ModelingBottleneck AnalysisScaling MetricsAnalytical SimulationArchitecture DirectionTechnical Strategy DevelopmentHigh-Performance Systems Design

Soft Skills

Clear CommunicationSound JudgmentInfluence Across TeamsMentoringBuilding Technical Communities

Certifications & Qualifications

MSEEMSCEPhD

Industry Keywords

AI ApplicationsHPCAccelerated ComputingSystem-Level Trade-OffsPerformance TargetsInvestment PrioritiesWorkload AlgorithmsData MovementTechnical CommunitiesEmerging Technology Opportunities

About the role

Key responsibilities & impact

Define the multi-generation strategy for application scaling across DRAM, NVLink, C2C, compute, and the supporting software stack.
Translate the behavior of important AI, HPC, and accelerated computing applications into architectural requirements, performance targets, and investment priorities.
Build a clear view of how bottlenecks shift as workloads scale across dies, GPUs, nodes, model sizes, data sets, and communication patterns.
Evaluate system-level trade-offs across bandwidth, latency, capacity, topology, coherence, power, area, cost, programmability, and resiliency.
Establish common workload scenarios, scaling metrics, models, and decision frameworks.
Identify architectural discontinuities and emerging technology opportunities.

Requirements

What you’ll need

MSEE, MSCE, PhD, or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
18+ years of relevant industry or academic experience, including experience setting architecture direction for complex, high-performance systems.
Deep understanding of system performance and scaling, including interactions among DRAM behavior, high-bandwidth fabrics such as NVLink, and C2C communication.
Strong application-level intuition, including the ability to connect workload algorithms, parallelism, communication, locality, and data movement to architecture choices and measurable outcomes.
Experience with workload characterization, analytical or simulation-based performance modeling, bottleneck analysis, and architecture trade-off evaluation.
Demonstrated ability to create and advance a multi-generation technical strategy through influence across silicon, systems, software, and application teams.
Clear communication and sound judgment in ambiguous technical areas, with the ability to explain complex system trade-offs to specialists and executive leaders.
Experience mentoring senior engineers into broader architecture leadership roles and building strong technical communities.

Benefits

Comp & perks

equity
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