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NVIDIA

Senior ASIC Design Engineer

NVIDIA

ASIC Design Engineer responsible for the implementation of GPU sub-system modules at NVIDIA. Making architectural trade-offs and delivering fully verified designs with a key design team.

Posted 7/28/2026full-timeSanta Clara • California, North Carolina • 🇺🇸 United StatesSenior💰 $168,000 - $264,500 per yearWebsite

Core Competencies

Role fit
Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in ASIC design and development, with a strong focus on micro-architecture and RTL implementation in Verilog. Proficient in collaborating with cross-functional teams to ensure successful post-silicon validation and design verification.

Highest-signal resume keywords
ASIC Design and DevelopmentMicro-Architecture and RTL ImplementationVerilog ProgrammingDigital Systems and VLSI DesignPost-Silicon Validation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills
ASIC Design FlowRTL DesignLogic SynthesisTiming AnalysisDFTPython ProgrammingPerl ProgrammingC/C++ ProgrammingComputer ArchitectureCMOS Circuits
Soft Skills
Analytical SkillsDebugging SkillsInterpersonal SkillsTeam Collaboration
Tools & Technologies
PCI-ExpressCXL ProtocolECOFloor-PlanningLab Debug
Certifications & Qualifications
Masters Degree in Electrical EngineeringMasters Degree in Computer Engineering
Industry Keywords
VLSI DesignComputer ArithmeticArbitersSchedulingSynchronizationBus ProtocolsInterconnect NetworksCaches

Tech Stack

Tools & technologies
PerlPython

About the role

Key responsibilities & impact
  • As a key member of the Design team, you will be responsible for the implementation of GPU sub-system modules.
  • Make architectural trade-offs based on features, performance requirements and system limitations.
  • You are expected to own micro-architecture, implement RTL, and deliver a fully verified, synthesis/timing clean design.
  • Support post-silicon validation activities.
  • Work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.

Requirements

What you’ll need
  • Masters Degree (or equivalent experience) in Electrical Engineering or Computer Engineering.
  • 8+ years of proven experience working on ASIC design and development.
  • Experience in micro-architecture and RTL development of complex designs in Verilog.
  • Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required.
  • Understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
  • Prior experience with arbiters, scheduling, synchronization & bus protocols, interconnect networks, and/or caches is desirable.
  • Knowledge of PCI-Express (Gen 3 and above) or CXL protocol is very helpful; your firsthand design experience on it is a big plus.
  • Python, Perl and C/C++ programming language experience desirable.
  • Good debugging and analytical skills.
  • Strong interpersonal skills and ability & desire to work as a great teammate.

Benefits

Comp & perks
  • equity
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