Senior ASIC Physical Design Engineer, Netlisting

NVIDIA

Senior ASIC Physical Design Engineer driving physical design for CPUs and GPUs at NVIDIA. Focus on netlist-related aspects and ensure timing convergence and implementation.

Posted 7/23/2026full-timeSanta Clara • California, Texas • 🇺🇸 United StatesSenior💰 $136,000 - $218,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in physical design of CPUs, GPUs, and SoCs, with a strong focus on logic equivalence checking, timing analysis, and netlist quality. Proficient in using industry-standard EDA tools and programming languages for effective design and implementation.

Highest-signal resume keywords

Logic Equivalence CheckingStatic Timing Analysis (STA)Clock-Domain-Crossing CheckingLogic SynthesisProgramming in Perl, TCL, Make, Python

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Physical DesignTiming ConvergenceTiming Constraints GenerationECO GenerationMTBF AnalysisRTL/Logic DesignNetlist Quality ChecksAsynchronous CheckingFull-Chip DesignBlock-Level Design

Tools & Technologies

Industry-Standard EDA ToolsIn-House Tools

Industry Keywords

Electrical EngineeringComputer EngineeringSoC DesignHigh-Frequency DesignLow-Power Design

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

Requirements

What you’ll need

BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience.
Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools.
Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools.
Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
Expertise and in-depth knowledge of industry standard EDA tools in related fields.
Proficiency in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.

Benefits

Comp & perks

equity
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