Senior Software R&D Engineer, VLSI Physical Design

NVIDIA

Senior R&D Software Engineer developing VLSI Physical Design Algorithms at NVIDIA. Innovating optimization engines for improved chip frequency and power consumption.

Posted 7/23/2026full-timeAustin • California, Texas • 🇺🇸 United StatesSenior💰 $168,000 - $310,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in VLSI algorithms development, particularly in C++, with a strong focus on timing optimization and power minimization. Proven ability to innovate and implement optimization solutions while collaborating effectively with design teams.

Highest-signal resume keywords

VLSI Algorithms DevelopmentC++ ProgrammingTiming OptimizationDesign Implementation ToolsStrong Communication Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

VLSI AlgorithmsC++Gate-Level SizingPower MinimizationECO RoutingIncremental Parasitic ExtractionCell LegalizationBufferingUseful Clock SkewTiming Constraints

Soft Skills

Strong CommunicationInterpersonal Skills

Tools & Technologies

ICC2InnovusPrimeTimeTempusStarRCPerlTclPython

Certifications & Qualifications

BS in Electrical EngineeringMS in Electrical EngineeringPhD in Electrical EngineeringEquivalent Experience in Computer Science

Industry Keywords

Chip FrequencyPower ConsumptionInterconnect ModelsCrosstalkGlitchesIR DropTiming CornersCongestion

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Invent new optimization engines that fuse traditionally independent engines with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.
Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.
Own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

Requirements

What you’ll need

BS, MS, PhD or equivalent experience in Electrical Engineering or Computer Science
6+ years in VLSI algorithms development using C++
Strong understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.
Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python
Strong communication and interpersonal skills

Benefits

Comp & perks

Eligible for equity and benefits