NVIDIA

Senior ASIC Physical Design Engineer, Netlisting

NVIDIA

full-time

Posted on:

Location Type: Office

Location: Santa Clara • California, Texas • 🇺🇸 United States

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Salary

💰 $136,000 - $264,500 per year

Job Level

Senior

Tech Stack

PerlPython

About the role

  • You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
  • Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

Requirements

  • BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience.
  • Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools.
  • Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
  • Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools.
  • Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
  • Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
  • Expertise and in-depth knowledge of industry standard EDA tools in related fields.
  • Proficiency in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.
Benefits
  • equity
  • benefits 📊 Resume Score Upload your resume to see if it passes auto-rejection tools used by recruiters Check Resume Score

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard skills
logic equivalence checkingtiming closureclock-domain-crossing checkingMTBF analysislogic synthesisStatic Timing Analysis (STA)timing constraints generationtiming convergenceprogramming languagesscripting languages
Certifications
BS in Electrical EngineeringBS in Computer EngineeringMS in Electrical EngineeringMS in Computer Engineering