ASIC Clocks Design Engineer – New College Grad

NVIDIA

ASIC Clocks Design Engineer designing GPU and CPU clocking for NVIDIA chips. Collaborating with multiple teams and architecting clock domains to meet design requirements.

Posted 6/4/2026full-timeSanta Clara • California, Texas • 🇺🇸 United StatesMid-LevelSenior💰 $100,000 - $166,750 per yearWebsite

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Architecting the clock domain to satisfy functional, physical and testing design requirements.
Engage with multiple teams and design the GPU or CPU clocks.
Improve Power, Performance, and Area (PPA) of NVIDIA chips by evaluating trade-offs.
Collaborate with Physical design and timing team to evaluate Clocking concerns.
Deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams.
Get involved in end-to-end cycle of ASIC execution starting from micro-arch.

Requirements

What you’ll need

Bachelor's degree or higher in Electrical Engineering (or equivalent experience).
Understanding of logic optimization techniques and PPA trade-offs.
Shown ability to collaborate with multiple teams.
Experience in RTL design (Verilog), verification and logic synthesis.
Strong coding skills in Python or other industry-standard scripting languages.

Benefits

Comp & perks

equity
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Hard Skills & Tools

RTL designVeriloglogic synthesislogic optimization techniquesPPA trade-offsPythonscripting languages

Soft Skills

collaboration

Certifications

Bachelor's degree in Electrical Engineering