Software R&D Engineer, Digital Logic Synthesis

NVIDIA

EDA Software R&D Engineer at NVIDIA developing algorithms for digital logic optimization and RTL synthesis. Collaborating within design teams to explore innovations in AI hardware optimization.

Posted 5/16/2026full-timeSanta Clara • California, Texas • 🇺🇸 United StatesMid-LevelSenior💰 $116,000 - $218,500 per yearWebsite

About the role

Key responsibilities & impact

Invent and develop new algorithms for RTL synthesis, digital logic optimization, graph-based RTL traversal, analysis, and manipulation.
Build physical-aware synthesis techniques using placement/congestion/timing feedback to improve PPA.
Develop strategies for rapidly analyzing the RTL change impact on timing, power, area, and impact to DFT, clocking, and power delivery on design.
Prototype and evaluate ML methods (e.g., GNNs, RL, models) to guide optimization decisions; integrate successful approaches into production.
Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight.
As a team, own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

Requirements

What you’ll need

MS or PhD in Electrical Engineering or Computer Science (or equivalent experience)
Experience with EDA software and/or VLSI flows with focus in logic synthesis or digital optimization
Strong CS fundamentals and modern C++ experience (templates/STL, concurrency libraries, profiling and performance optimization, data structures, algorithms, performance, concurrency, testing)
Solid understanding of RTL (Verilog/SystemVerilog) and digital design concepts (timing, clocking, DFT basics, power intent)
Experience in EDA techniques, including logic synthesis, global route, static timing analysis, power & area optimization and SAT solvers

Benefits

Comp & perks

equity
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Hard Skills & Tools

algorithmsRTL synthesisdigital logic optimizationgraph-based RTL traversalphysical-aware synthesisC++VerilogSystemVerilogstatic timing analysisEDA techniques

Soft Skills

team collaborationproblem-solvingcommunication

Certifications

MS in Electrical EngineeringPhD in Computer Science