Senior Power Integrity Methodology CAD Engineer

NVIDIA

Senior Power Integrity Methodology CAD Engineer developing methodologies for rail analysis and signoff at NVIDIA. Crafting workflows and solutions for power and noise analysis across multiple projects.

Posted 5/11/2026full-timeSanta Clara • California, Texas • 🇺🇸 United StatesSenior💰 $168,000 - $310,500 per yearWebsite

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Developing physical design methodologies for rail analysis and signoff
Responsible for coming up with unique and creative solutions for pioneering IR analysis and signoff that are needed for NVIDIA chips
Crafting workflows and tool methodologies for power and noise analysis across multiple projects

Requirements

What you’ll need

Master's degree or equivalent experience in Electrical Engineering or related field
Minimum 5+ years of experience in EMIR flow methodology development and support
Strong understanding of all aspects of EMIR analysis and signoff
Familiar with hierarchical design approach and hierarchical signoff
Experience with shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle
Ability to collaborate across teams: Strong interpersonal, communication and teamwork skills, with a track record of working closely with hardware and design teams to facilitate EMIR signoff
Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++

Benefits

Comp & perks

equity
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Applicant Tracking System Keywords

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Hard Skills & Tools

EMIR flow methodology developmentEMIR analysishierarchical design approachhierarchical signoffshift-left methodologiesTCLPerlPythonC++

Soft Skills

interpersonal skillscommunication skillsteamwork skills

Certifications

Master's degree in Electrical Engineering