Senior ASIC RTL Integration, Netlisting Engineer

NVIDIA

ASIC RTL Integration and Netlisting Engineer at NVIDIA driving the design of high-frequency and low-power CPUs, GPUs, and SoCs. Responsibilities include RTL integration, synthesis, and netlist deliverables.

Posted 5/11/2026full-timeSanta Clara • California, North Carolina, Oregon, Texas • 🇺🇸 United StatesSenior💰 $168,000 - $264,500 per yearWebsite

About the role

Key responsibilities & impact

Drive physical design integration and implementation of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level
Drive RTL integration, synthesis, along with all physical netlist deliverables across various milestones
Drive formal equivalence checking, netlist quality checks, asynchronous checking including clock domain crossing checks and MTBF analysis, etc.

Requirements

What you’ll need

BS (or equivalent experience) in Electrical or Computer Engineering with 8+ years’ experience or MS (or equivalent experience) with 5+ years’ experience in RTL integration and netlisting domains.
Strong understanding of RTL and RTL hierarchy and associated infrastructures
Hands on experience with logic synthesis and associated verification such as equivalence checking
Background in gate level netlist verification and completeness with respect to power, testability, etc
Expertise and in-depth knowledge of industry standard EDA tools

Benefits

Comp & perks

equity
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Hard Skills & Tools

RTL integrationlogic synthesisnetlistingformal equivalence checkingnetlist quality checksasynchronous checkingclock domain crossing checksMTBF analysisgate level netlist verificationtestability