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ASIC Design, STA Engineer
NVIDIAASIC STA Engineer developing industry leading high-speed communication devices for AI platforms at NVIDIA. Involve in full chip STA convergence and collaborating with design teams in a supportive environment.
About the role
Key responsibilities & impact- Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.
- Take part in top level floor plan and clock planning.
- Optimize, together with CAD signoff flows and methodologies.
- Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence.
- Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.
Requirements
What you’ll need- B.SC./ M.SC. in Electrical Engineering/Computer Engineering
- 3+ years of experience in physical design and STA
- Proven experience in RTL2GDS and STA design and convergence
- Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)
- Hands on STA experience from early stages to signoff using Synopsis Primetime.
- Deep knowledge in timing concepts required.
Benefits
Comp & perks- Diverse, supportive environment
- Opportunities to learn and evolve.
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
STA convergencephysical designRTL2GDStiming integrationconstraints definitionoptimizationtiming concepts
Certifications
B.Sc. in Electrical EngineeringM.Sc. in Electrical EngineeringB.Sc. in Computer EngineeringM.Sc. in Computer Engineering