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About the role
Key responsibilities & impact- Verify the design and implementation of SerDes IPs
- Build reusable bus functional models, monitors, checkers and scoreboards
- Define the verification scope
- Develop the verification infrastructure
- Write and execute test plan to verify design
Requirements
What you’ll need- Bachelor or Master's Degree in Electrical Engineering, Computer Science, or Computer Engineering
- At least 5 years of proven experience
- Background in verification at Unit/Sub-system/SOC level
- Expertise in SystemVerilog
- Experience using random stimulus along with functional coverage and assertion-based verification methodologies
- Experience in verification methodologies like UVM/VMM
- Exposure to industry standard verification tools for simulation and debug
Benefits
Comp & perks- Competitive salaries
- Generous benefits package
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
SystemVerilogUVMVMMfunctional coverageassertion-based verificationverification infrastructurebus functional modelsmonitorscheckersscoreboards
Certifications
Bachelor's Degree in Electrical EngineeringMaster's Degree in Electrical EngineeringBachelor's Degree in Computer ScienceMaster's Degree in Computer ScienceBachelor's Degree in Computer EngineeringMaster's Degree in Computer Engineering
