Define and implement SCAN, MBIST, and JTAG debug structures, applying sophisticated DFT techniques to drive post-Si testing plans
Drive the creation of ATPG and MBIST test vectors
Build DFT timing constraints and partner with the Physical Design and STA sign-off team to ensure timing closure in DFT mode
Work closely with the post-silicon team to bring up test patterns on silicon, ensuring flawless bringup
Collaborate with the CAD methodology team to introduce innovative and intelligent AI driven optimizations, improving efficiency in DFT implementation

Requirements

Bachelor's or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience)
5+ years of industry experience in DFT for high-performance ASICs
Practical experience with SCAN/MBIST/Test generation tools and processes for large SoC/ASIC
Domain expertise in DFT techniques such as ATPG, test pattern translation, yield learning, scan compression, MBIST, IEEE 1500 standard, and LBIST
Familiarity with ATPG Streaming SCAN Network (SSN) implementation
Experience with UDFMs like Cell Aware and Small Delay Defect
Consistent track record in yield estimation and test optimization
Experience working with real silicon in the lab and debugging DFT test sequences on ATE to resolve silicon issues
Solid understanding of RTL to GDS methodologies and formal equivalence
Excellent coding skills in Tcl and Python
Outstanding interpersonal and organizational skills with a strong desire to work as part of a team with varied strengths.

Benefits

equity
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Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

DFT techniquesATPGMBISTJTAGTclPythontest generationtiming closurescan compressionyield estimation

Soft Skills

interpersonal skillsorganizational skillsteam collaboration