NVIDIA

Senior STA Engineer, Sub-Chip

NVIDIA

full-time

Posted on:

Location Type: Office

Location: Tel Aviv • Israel

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Job Level

Senior

About the role

  • Perform advanced Static Timing Analysis (STA) at chiplet and FC level.
  • Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
  • Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.
  • Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.

Requirements

  • B.SC./ M.SC. in Electrical Engineering.
  • At least 5+ years of hands-on STA experience.
  • Experience in Prime Time and signoff methodologies.
  • Excellent leadership capabilities.
Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools
Static Timing AnalysisPrime Timetiming pathssdc generationtiming ecos generationtiming closurequality approvalpre-layout STA modelsignoff methodologies
Soft Skills
leadership capabilities
Certifications
B.Sc. in Electrical EngineeringM.Sc. in Electrical Engineering