Verify the design and implementation of inference accelerator
Responsible for verification of the ASIC design, architecture, reference models and micro-architecture using advanced verification methodologies
Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design
Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks
Implement and optimize automated verification flows to improve productivity and efficiency
Stay updated on the latest trends and advancements in ASIC design verification and incorporate innovative techniques into the verification process

Requirements

Bachelors Degree in EE, CS or CE (or equivalent experience) and 8+ years of relevant industry experience
Background with building block and SoC level testbench utilizing strong debugging and analytical skills
Experience in verification using random stimulus along with functional coverage, assertion-based verification methodologies and tools
Expertise in SystemVerilog and Universal Verification Methodology (UVM)
Experience with design and verification tools (VCS, Verdi or equivalent)
Background in UPF power verification is a plus
Experience in netlist and DFT verification is a plus
Perl/Python and C/C++ programming language experience desirable
Knowledge of ASIC design flow, from specification to GDS
Knowledge of applying machine learning to ASIC verification flow

Benefits

Competitive salaries
Generous benefits package
Equity

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

ASIC design verificationSystemVerilogUniversal Verification Methodology (UVM)random stimulus verificationfunctional coverageassertion-based verificationdebuggingPerlPythonC/C++

Soft Skills

analytical skillscollaborationcommunicationproblem-solvinginnovation