Design Verification Engineer – PCIE
NVIDIA
full-time
Posted on:
Location Type: Office
Location: Taipei • Taiwan
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About the role
- Responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
- Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
- Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
- Collaborate with architects, designers, and pre and post silicon verification teams to accomplish tasks.
Requirements
- B.Tech./M.Tech. with 2+ years of relevant experience
- Experience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog
- Background with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
- Experience in developing and working in functional coverage based constrained random verification environments
- Experience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug
Benefits
- Competitive salaries
- Generous benefits package
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
VerilogSystemVerilogUVMVMMfunctional coverageconstrained random verificationASIC design verificationtest plan developmentverification infrastructurePCIE controllers
Soft Skills
collaborationcommunication
Certifications
B.Tech.M.Tech.