Senior ASIC Verification Engineer, Coherent High Speed Interconnect

NVIDIA

full-time

Posted on: 1/26/2026

Location Type: Office

Location: Hsinchu • Taiwan

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About the role

Responsible for verification of high-speed coherent interconnect design, architecture, golden models, and micro-architecture using sophisticated verification methodologies
You'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design
Collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks

Bachelors or Master’s Degree (or equivalent experience)
5+ years of relevant verification experience
Experience in architecting test bench environments for unit level verification
Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
Prior Design or Verification experience of Coherent high-speed interconnects
Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful
Strong background developing TB's from scratch using SV and UVM methodology is desired
C++ programming language experience, scripting ability and an expertise in System Verilog
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
Strong debugging and analytical skills
Experienced communication and interpersonal skills are required
A history of mentoring junior engineers and interns a huge plus

Benefits

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

verification methodologiestest benchesBFMscheckersmonitorsSystem VerilogUVM methodologyC++random stimulusfunctional coverage

Soft Skills

communication skillsinterpersonal skillsanalytical skillsdebugging skillsmentoring