You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, chiplet level, and/or full chip level.
Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets.
Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

Requirements

BS (or equivalent experience) in Electrical or Computer Engineering with 8 years experience or MS with 4+ years experience in Synthesis and Timing.
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
Expertise in physical design and optimization e.g., placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs.
Background in logic synthesis and/or logical equivalence checking (LEC).
Expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus).
Proficiency in Python, Tcl and Make for automation and scripting tasks.

Benefits

equity
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Applicant Tracking System Keywords

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Hard Skills & Tools

Static Timing Analysistiming constraints generationtiming convergencephysical designplacementroutinglogic synthesislogical equivalence checkingECO implementationcrosstalk analysis