Senior ASIC Verification Engineer, Coherent High Speed Interconnect
NVIDIA
full-time
Posted on:
Location Type: Hybrid
Location: Santa Clara • California, Massachusetts, Oregon, Texas • 🇺🇸 United States
Visit company websiteSalary
💰 $136,000 - $264,500 per year
Job Level
Senior
About the role
- verify the design and implementation of our innovative high speed coherent interconnects for our mobile SoCs and GPUs
- be responsible for verification of high-speed coherent interconnect design, architecture and golden models
- be responsible for micro-architecture using sophisticated verification methodologies
- understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design
- collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks
Requirements
- Bachelors or Master’s Degree (or equivalent experience)
- 3+ years of relevant verification experience
- Experience in architecting test bench environments for unit level verification
- Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
- Prior Design or Verification experience of Coherent high-speed interconnects
- Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful
- Strong background developing TB's from scratch using SV and UVM methodology is desired
- C++ programming language experience, scripting ability and an expertise in System Verilog
- Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
- Strong debugging and analytical skills
- Experienced communication and interpersonal skills are required
- A history of mentoring junior engineers and interns a huge plus.
Benefits
- equity
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Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
verificationmicro-architecturetest benchesrandom stimulusfunctional coverageassertion-based verificationSystem VerilogC++UVM methodologydebugging
Soft skills
communicationinterpersonalanalyticalmentoring
Certifications
Bachelor's DegreeMaster's Degree