Senior Mixed Signal Design Engineer
NVIDIA
full-time
Posted on:
Location Type: Office
Location: Hsinchu • 🇹🇼 Taiwan
Visit company websiteJob Level
Senior
Tech Stack
PerlPython
About the role
- Work with analog designers to create accurate systemVerilog model of analog components such as closed-loop PLL, Rx CTLE, SAR ADC and also optics components.
- You’ll work with system architects, digital designers to define and verify the system architecture specification and refine adaptation algorithms.
- Help in streamlining workflows with proper scripts to increase efficiency and enables reusability
- Be actively involve in silicon bringup, build scripts that can be used for debug, QA, characterization and ATE
Requirements
- B.S. or MS degree in Electrical Engineering or equivalent experience
- 5+ years of experience working in high-speed I/O digital design, knowledge at protocol level (SATA, PCIE, USB) preferred
- Have a deep understanding of Verilog or SystemVerilog, logic design and circuit modeling for mixed-signal blocks
- Deep understanding of high-speed Serdes/PLL analog circuit design.
- Proven experience with custom digital circuit design and adaptation algorithms, such as DFE, CTLE, CDR, and offset cancellation
- Have a strong background in Perl and Python scripting
- Background in computer architecture and deep learning is a plus.
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
SystemVerilogVeriloghigh-speed I/O digital designprotocols (SATA, PCIE, USB)mixed-signal blocksSerdesPLLDFECTLECDR
Certifications
B.S. in Electrical EngineeringMS in Electrical Engineering