Senior Technical Staff Engineer – Design, IO

Staff/Sr. Staff IO Design Engineer developing storage and memory controller SoC products for Microchip.

Posted 6/4/2026full-timeSan Jose • California • 🇺🇸 United StatesSenior💰 $91,000 - $232,000 per yearWebsite

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Hard Skills

pad ring planningIO cell placementbump map definitionVerilogSystem VerilogJTAGBoundary ScanDFT methodologiesscripting

Soft Skills

analytical skillscommunication skillsdocumentation skills

Tools & Technologies

Orbit IOISPEDA tools

Industry Keywords

SoC designsIEEE 1149.1SerDesDDRPCIeCXLphysical design hand-offpost-silicon debugTAP controller operation

Key responsibilities & impact

Design planning of pad rings and package substrates, bump pattern construction
Dynamically define and optimize pad ring connectivity
Work with CFTs (Cross-Functional Team) on the deliverables (DEF, Verilog netlist etc.,)
Interface with and support Architect, PD, PE, technology development and foundries teams
Support JTAG TAP controller integration and implementation across SoC designs, ensuring IEEE 1149.1 compliance and proper JTAG signal connectivity in collaboration with the DFT team
Collaborate with CFTs on TAP controller operation, scan-enable path handling, and post-silicon debug requirements
Support Verification, Emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds

What you’ll need

B.S or M.S degree in electrical engineering with 12+ years related experience
Hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs
Knowledge of IO library cells, IO standards, and PHY-level IO interfaces (SerDes, DDR, PCIe, CXL)
Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent)
Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment) for physical design hand-off
Experience with Verilog/System Verilog is required
Basic to intermediate knowledge of JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation
Hands-on experience with DFT methodologies is a plus and considered equivalent familiarity
Familiarity with JTAG-based post-silicon debug flows and bring-up strategies for SoC IO validation
Experience with boundary scan cell behavior and test access port (TAP) signal verification is a plus
Scripting experience or knowledge is a plus
Excellent analytical, communication (written and verbal), and documentation skills.

Comp & perks