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Formal Verification Engineer
LUBIS EDAFormal Verification Engineer taking ownership of formal deliverables in a fast-growing semiconductor startup. Creating verification strategies to ensure chips work flawlessly before production.
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
RTLSVAformal verificationcachespipelined processorsDMAsNoCs
Soft Skills
independent workrequirement clarificationend-to-end ownership
Tools & Technologies
JasperVCFQuesta FormalOnespin
Industry Keywords
formal deliverableproof closuresign-off artifactsverification strategymaintainable SVAclean formal environment
About the role
Key responsibilities & impact- Own a defined formal deliverable end–to–end
- Work independently in known contexts
- Drive proof closure and hand over sign–off artifacts
- Clarify requirements and co-define the verification strategy
- Produce maintainable SVA and a clean formal environment
Requirements
What you’ll need- Proven experience delivering formal results on non–trivial RTL (e.g., caches, pipelined processors, DMAs, NoCs)
- Strong SVA skills
- Hands-on formal tool experience (e.g.: Jasper, VCF, Questa Formal/Onespin)
- Reliable end–to–end ownership in a defined scope
Benefits
Comp & perks- Flexible work arrangements
- Professional development