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Senior Formal Verification Engineer
LUBIS EDASenior Formal Verification Engineer at LUBIS redefining semiconductor verification through structured automation and mentoring. Leading project outcomes and strategies for complex chip designs.
About the role
Key responsibilities & impact- Own complex outcomes (weeks to a quarter).
- Turn ambiguity into a plan, drive convergence and debug to closure.
- Set a high bar for property quality, constraint hygiene, and non‑vacuity.
- Drive convergence with sound modeling judgment (abstraction, cutpoints/invariants, assume‑guarantee).
- Take ownership of scope estimation and execution planning, turning unclear requests into a realistic plan (milestones, effort, risks).
- Lead first projects technically with low-to-medium complexity, incl. mentoring others.
Requirements
What you’ll need- Strong track record delivering formal outcomes on complex designs.
- Deep SVA + modeling judgment + convergence/debug expertise.
- Proven track record of defining a sound verification strategy independently (scoping, risk assessment, assumptions/constraints, and closure criteria).
Benefits
Comp & perks- Health insurance
- Professional development opportunities
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
SVAmodelingverification strategyscope estimationexecution planningrisk assessmentassumptionsconstraintsclosure criteriadebugging
Soft Skills
ownershipleadershipmentoringplanningconvergencejudgmentcommunicationproblem-solvingadaptabilityattention to detail