Design, implement, and verify digital logic circuits and systems.
Develop and maintain hardware description language (HDL) code, with a primary focus on Verilog/SystemVerilog
Work on FPGA/ASIC design, synthesis, and verification, including hands-on RTL coding.
Complex cryptographic IP block development and the implementation of patent-pending DPA countermeasures across front-end design, including microarchitecture specification, RTL code development, and verification.
Collaborate with software, hardware, and verification engineers in design integration and testing.
Perform timing, power, performance, area analysis, and optimization to meet requirements.
Participate in design and code reviews and provide constructive feedback.
Document design specifications and interfaces.
Stay up-to-date with the latest industry trends and technologies related to digital logic design.
Requirements
Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
4–5 years of hands-on experience in logic design, microarchitecture, and RTL coding in Verilog.
Proven experience with VCS, Verdi, and Spyglass—or similar tools.
Experience with FPGA design and implementation, including synthesis, place, and route.
Familiarity with ASIC design and/or verification methodologies.
Ability to write detailed, clear microarchitecture and verification reports
Familiarity with CAD for ASIC design (Synopsys or Cadence).
Familiarity with formal verification between RTL and Netlist.
Familiarity with modern cryptography.
Strong problem-solving skills and attention to detail.
Excellent communication and teamwork skills.
Ability to work independently and manage multiple tasks effectively.