RTL Design Engineer

Inabia Solutions and Consulting, Inc.

RTL Design Engineer responsible for the full micro-architecture and RTL design lifecycle. Engaging in custom silicon development with minimal supervision in a remote contract environment.

Posted 7/15/2026contractRemote • 🇺🇸 United StatesJuniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RTL design using SystemVerilog and Verilog, with a strong ability to define micro-architecture and integrate digital blocks. Proficient in managing the full project lifecycle and collaborating with design verification teams for effective closure and debugging.

Highest-signal resume keywords

RTL Design Using SystemVerilogMicro-Architecture DefinitionIP IntegrationMemory Controllers (HBM, DDR4, DDR5)Sign-Off Flows (CDC, RDC)

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DesignSystemVerilogVerilogDigital Block Control LogicCustom RTL Blocks DesignSoC IntegrationBlock-Level OwnershipClock Domain Crossing (CDC)Reset Domain Crossing (RDC)Synthesis Readiness Checks

Soft Skills

Independent OperationCollaboration

Industry Keywords

Digital Subsystem DesignDesign VerificationProject Lifecycle Ownership

About the role

Key responsibilities & impact

Own micro-architecture definition derived from high-level functional specifications
Develop and implement RTL for complex digital blocks using SystemVerilog/Verilog
Drive digital block control logic and IP integration
Participate in subsystem-level architecture alignment discussions
Support design sign-off activities including CDC, RDC, lint, and synthesis readiness checks
Collaborate closely with Design Verification (DV) teams for closure and debug
Take full project lifecycle ownership with minimal supervision

Requirements

What you’ll need

Strong, current expertise in RTL design using SystemVerilog and/or Verilog
Demonstrated ability to independently define micro-architecture from functional specs
Recent hands-on experience designing custom RTL blocks such as controllers, DMAs, or SoC bus bridges
Solid understanding of memory controllers, including HBM, DDR4, or DDR5
Experience with SoC integration and digital subsystem design
Proficiency with IP integration and block-level ownership
Working knowledge of sign-off flows including CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing)
Experience designing IPs with multiple clock domains
Ability to operate independently with no ramp-up time required

Benefits

Comp & perks

Flexible work arrangements