FPGA Developer, Digital Signal Processing

HR Buddys

FPGA developer focusing on digital signal processing for a technology startup creating premium hardware. Involved in HDL design and implementation, and digital signal processing development.

Posted 7/28/2026full-timeRemote • 🇺🇸 United StatesMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in HDL design and implementation, particularly in VHDL, with a strong focus on digital signal processing algorithms and FPGA design. Proficient in timing analysis, design optimization, and the development of high-speed I/O interfaces.

Highest-signal resume keywords

HDL Design in VHDLDigital Signal Processing (IIR/FIR Filters, FFT)FPGA Design ExperienceTiming Analysis and OptimizationSimulation Tools (ModelSim)

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

HDL DesignVHDL ImplementationDigital Signal ProcessingTiming AnalysisFPGA DesignTestbench DevelopmentHigh-Speed I/O InterfacesSoC IntegrationResampling AlgorithmsControl Engineering

Tools & Technologies

AMD VivadoModelSimReal-Time Fieldbuses (EtherCAT, PROFINET)Integrated SoCs (AXI/Avalon, EMIO)Soft Processors (MicroBlaze, Nios)

Certifications & Qualifications

Bachelor’s Degree in STEM Field

Industry Keywords

FPGA DesignDigital Signal ProcessingTiming ClosureNumerical StabilityResource Efficiency

About the role

Key responsibilities & impact

HDL design and implementation
Implementation of HDL designs in VHDL.
Design and implementation of well-structured, reusable, and well-documented RTL modules for the measurement signal chain.
Timing analysis and design optimization up to timing closure.
Design and implementation of digital signal processing algorithms, in particular: IIR/FIR filters, decimation and resampling, frequency-domain analysis (FFT).
Implementation of the DSP chain with a focus on accuracy, numerical stability, and resource efficiency on the FPGA.
Design and implementation of high-speed I/O interfaces to ADCs, processor systems, real-time fieldbuses and other devices.
Contribution to the design of I/O and SoC integration for the first development phase, together with the Chief Architect.
Design and implementation of testbenches for simulation, testing and verification.
Documentation of designs and verification results to ensure reliable interfaces and compliance with specifications.

Requirements

What you’ll need

Bachelor’s degree or equivalent qualification in a STEM field.
At least 5 years of professional experience in FPGA design.
Demonstrable expertise in digital signal processing (IIR/FIR filters, FFT, resampling algorithms).
Confident handling of HDL design in VHDL.
Solid understanding of timing constraints and optimization techniques for timing closure.
Experience with simulation tools such as ModelSim and with established verification techniques.
Proficient with AMD Vivado.
Business-fluent English (C1+) OR business-fluent German (C1+) with English at B2 level.
Nice to have: Experience with real-time fieldbuses (EtherCAT, PROFINET).
Experience with integrated SoCs (AXI/Avalon, EMIO, etc.).
Experience with soft processors (MicroBlaze, Nios, Embedded C).
Knowledge of control engineering.
Experience with high-speed techniques for serial and parallel I/O.

Benefits

Comp & perks

Freedom to shape the role from day one: You will build the FPGA development function within the company and shape the design culture.
Direct access to the Chief Architect and founding team.
Short communication lines, clear decision-making, no organizational politics.
Technically demanding work: Class-A power-quality measurement technology at the limits of what is technically feasible.
Market tailwinds: Data centers, the energy transition and EU regulation provide significant momentum in the power-quality segment.
Attractive compensation package with a fixed salary and variable components.
Growth perspective: As the function expands, development into an FPGA/DSP team is explicitly planned, including I/O and fieldbus development.