Fraunhofer IIS

System on Chip Verification Engineer – all genders

Fraunhofer IIS

full-time

Posted on:

Location Type: Hybrid

Location: Erlangen • Germany

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Tech Stack

AssemblyPython

About the role

  • Play a key role in pre-silicon RTL verification of block and top-level SoC designs utilizing RISC-V architecture
  • Understand the nuances of RISC-V architectures and industry-standard low-power architectures to build block/chip level testbenches using best-in-class verification methodologies
  • Translate design specifications into comprehensive verification plans in collaboration with system architects
  • Develop and maintain reusable testbenches for IP/block-level verification and support IP integration verification
  • Create smart, constraint-random and directed test cases tailored to RISC-V SoCs
  • Build and analyze coverage models, and refine tests to close coverage gaps
  • Debug test failures, manage bug tracking, and ensure coverage closure
  • Lead verification reviews to uphold coding quality and best practices in SoC verification
  • Prepare, run, and evaluate regression runs

Requirements

  • University degree in (electrical) engineering, IT/computer science or another related field
  • Solid understanding of digital logic design and RISC-V-based SoC architecture
  • Proven experience with SystemVerilog and UVM-based verification environments
  • Very good English and good German language skills
  • Proactive and independent mindset
  • Nice to have: Familiarity with C / C++ programming, assembly and object-oriented languages such as Python
  • Knowledge of industry-standard interfaces and bus protocols (e.g., AXI)
  • Experience with IP verification methods, integration verification specific to RISC-V and embedded CPU verification
  • Interest in low power verification techniques and formal verification tools (e.g. JasperGold)
Benefits
  • Flexible working hours
  • Personal development opportunities
  • Room for creativity
  • Friendly and supportive working atmosphere
Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools
RISC-V architectureRTL verificationSystemVerilogUVMdigital logic designtestbenchesconstraint-random test casescoverage modelsdebuggingregression testing
Soft Skills
proactive mindsetindependent mindsetcollaborationcommunicationleadership
Certifications
university degree in electrical engineeringuniversity degree in IT/computer science