Senior Hardware Design Engineer
FortifyIQ
full-time
Posted on:
Location Type: Remote
Location: United States
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Job Level
About the role
- Define HW architecture and evaluate design trade-offs for performance, area, and power.
- Lead RTL development, integration, and verification throughout the design cycle.
- Partner with firmware and verification teams to ensure top-quality silicon delivery.
- Mentor and review junior engineers’ work, promoting best practices and technical excellence.
- Provide design-in and bring-up support, including technical expertise for customer-facing projects.
Requirements
- Strong command of SystemVerilog for RTL design and digital architecture.
- Experience using simulation tools such as Questa, Incisive, or VCS.
- Skilled in scripting (Python, Perl, Tcl) for automation and workflow optimization.
- Proven experience in ASIC or FPGA design, synthesis, and timing closure.
- Strong analytical thinking and communication skills, with the ability to manage complex priorities.
- 10+ years of relevant experience and a BSEE or MSEE degree.
- Expertise in ASIC synthesis, timing constraints, CDC/RDC methodologies preferred.
- Familiarity with UVM-based verification environments preferred.
- Experience with high-speed memory technologies (HBM, GDDR, LPDDR, DDR) preferred.
- Understanding of AMBA AXI or CHI protocols preferred.
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
SystemVerilogRTL designdigital architectureASIC designFPGA designsynthesistiming closurescriptingUVM-based verificationhigh-speed memory technologies
Soft skills
analytical thinkingcommunication skillsmentoringtechnical excellenceworkflow optimizationmanaging complex priorities
Certifications
BSEEMSEE