Functional Verification Engineer
Factorial
full-time
Posted on:
Location Type: Hybrid
Location: Barcelona • Spain
Visit company websiteExplore more
About the role
- Interfacing with architecture, design, physical implementation and software teams.
- Reading and analysing the system requirements and architecture requirement documents.
- Developing Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++.
- Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures.
- Creating and executing testcases to verify functionality, performance, and robustness in embedded C and SV.
- Identifying, isolating and debugging issues found during verification.
- Working closely with cross-functional teams to achieve verification closure.
Requirements
- Master Degree in relevant field.
- Min 5 years of experience in relevant field of Verification of complex SoC or IP.
- Experience in SystemVerilog/UVM SystemC/C++.
- Experience in Constrained random, Functional Coverage development, design debug.
- Experience in Formal Verification, UPF.
- Experience in HW-SW co-verification and simulation.
- Some previous experience in Firmware based verification is a good to have.
- Some knowledge of scripting languages like Bash/Perl/Python.
- Strong debugging and problem-solving skills, with the ability to effectively analyze and resolve complex verification issues.
- Good level of English, both written and spoken is mandatory.
Benefits
- Join an innovative team and experience company growth.
- Flexible schedule.
- Competitive compensation package.
- Hybrid work environment.
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
SystemVerilogUVMSystemCC++Constrained randomFunctional CoverageFormal VerificationUPFHW-SW co-verificationscripting languages
Soft Skills
debuggingproblem-solvinganalytical skillscommunication
Certifications
Master Degree