Factorial

Senior ASIC Engineer – Technical Lead

Factorial

full-time

Posted on:

Location Type: Hybrid

Location: Barcelona • 🇪🇸 Spain

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Job Level

Senior

About the role

  • Lead and contribute to full ASIC development flows, from system and RTL design to GDSII sign-off
  • Define and validate digital architectures, including RISC-V SoCs and domain-specific accelerators
  • Drive technical decisions related to RTL design, verification strategies, synthesis, P&R, and sign-off
  • Design, implement, and maintain FPGA-based prototypes to validate architectures, subsystems, and system-level functionality ahead of tape-out
  • Use FPGA prototyping as a vehicle for early software bring-up, performance evaluation, and risk reduction
  • Interface with foundries, EDA vendors, and external industrial partners during design, fabrication, and validation phases
  • Act as primary technical point of contact for hardware design and ASIC/SoC development contracts with public research centers and universities
  • Coordinate, supervise, and technically validate externally contracted hardware design activities, ensuring alignment with internal architectures, schedules, and quality requirements
  • Facilitate effective collaboration and technology transfer between internal engineering teams and public research institutions
  • Provide technical leadership and mentoring to junior engineers and project teams
  • Contribute to European collaborative R&D projects, representing the company in technical discussions with research institutes, universities, and industrial partners
  • Support technology scouting and evaluation of new process nodes, tools, and design methodologies

Requirements

  • Master’s degree in Electronics Engineering or a related field
  • 15+ years of experience in ASIC and SoC development within microelectronics environments
  • Proven experience covering the complete ASIC flow: RTL, synthesis, place & route, verification, and sign-off
  • Strong expertise in digital design languages (VHDL, Verilog, SystemVerilog)
  • Hands-on experience with FPGA prototyping, including architecture validation and system-level bring-up (Xilinx, Intel/Altera or equivalent)
  • Solid background in RISC-V architectures and complex SoC integration
  • Deep understanding of EDA tools and ASIC/FPGA design methodologies
  • Demonstrated ability to work effectively in collaborative R&D environments involving external stakeholders such as research institutes and universities
  • Excellent communication skills and ability to act as a technical interface between industrial and academic teams
  • Fluent in English; Spanish and/or Catalan are a plus.
Benefits
  • Flexible working conditions and hybrid work environment
  • Competitive remuneration aligned with seniority and expertise

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard skills
ASIC developmentRTL designGDSII sign-offdigital design languagesVHDLVerilogSystemVerilogFPGA prototypingRISC-V architecturesEDA tools
Soft skills
technical leadershipmentoringcollaborationcommunicationproject supervisiontechnical validationstakeholder engagementtechnology transferrisk reductioneffective collaboration
Certifications
Master’s degree in Electronics Engineering