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MTS – ASIC Silicon Debug, Device Technology & Yield Engineering
EightfoldMTS in ASIC Silicon Debug on silicon yield, reliability and quality improvements at Micron. Drive root-cause analysis and lead cross-functional collaborations for effective debugging.
About the role
Key responsibilities & impact- Lead end-to-end investigation of silicon yield loss, field returns, customer escalations, and reliability failures.
- Drive root-cause analysis for complex silicon issues spanning process, design, test, package, and system interactions.
- Develop hypothesis-driven debug strategies and coordinate cross-functional execution.
- Own resolution of critical yield and quality issues through containment, corrective actions, and prevention plans.
- Analyze device-level failure mechanisms and process sensitivities impacting ASIC functionality and yield.
- Partner with foundry teams to understand process variations, excursions, reliability risks, and technology limitations.
- Translate silicon learning into actionable design and process improvements.
- Lead root-cause investigations involving design-process interactions affecting SRAM, PCIe PHY, ONFI interfaces, SerDes, analog/mixed-signal circuits, and high-speed digital subsystems.
- Analyze silicon failures across transistor, circuit, block, die, package, and system levels.
- Drive post-silicon debug activities involving design teams, DFT, product engineering, quality, reliability, foundry, and customer support organizations.
- Develop silicon characterization plans to isolate process, design, and test-related contributors.
- Drive silicon learning feedback into next-generation ASIC architecture and design methodologies.
- Drive advanced FA activities including: FIB, SEM/TEM, EFA, OBIRCH, LVP, Emission microscopy, Physical cross-section analysis.
Requirements
What you’ll need- 12+ years of semiconductor industry experience.
- Strong background in advanced CMOS technology and silicon product development.
- Proven success leading yield improvement, RMA, and failure analysis efforts.
- Experience working directly with foundries and OSAT partners.
- Deep understanding of CMOS device physics and advanced semiconductor process technologies.
- Strong expertise in SRAM architecture, memory design fundamentals, memory margin analysis, and failure mechanisms.
- Strong understanding of high-speed interface technologies including PCIe, ONFI, SerDes, and clocking architectures.
- Experience with post-silicon debug and characterization of complex ASIC devices.
- Expertise in process-design interaction analysis and variation-aware design methodologies.
- Strong knowledge of: Signal Integrity (SI), Power Integrity (PI), Timing closure methodologies, Device variability and mismatch analysis, Reliability-induced failure mechanisms.
- Experience correlating: Wafer Acceptance Test (WAT), Electrical test data, Yield data, Reliability data, Failure Analysis results, Customer-return information.
Benefits
Comp & perks- Health insurance
- Paid time off