Principal DFT Engineer, HBM

Eightfold

Principal SoC DFT Engineer designing HBM base-die System-on-Chip architectures. Collaborating with multi-functional teams to implement robust test solutions for advanced semiconductor technology.

Posted 7/23/2026full-timeFolsom • California, Texas • 🇺🇸 United StatesLead💰 $146,000 - $309,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in SoC-level DFT implementation, including scan, MBIST, LBIST, and JTAG, while ensuring alignment with design constraints. Proficient in collaborating with cross-functional teams to optimize DFT solutions and support pre-silicon and post-silicon processes.

Highest-signal resume keywords

SoC DevelopmentDFT ImplementationScan InsertionATPG ConceptsEDA Tools Proficiency

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT Logic IntegrationScan InsertionMBIST ArchitectureLBIST ArchitectureBoundary ScanATPG ReadinessFull RTL-to-GDS FlowsScripting LanguagesDFT Rule ChecksCoverage Closure

Tools & Technologies

EDA ToolsSiemens ToolsSynopsys ToolsCadence Tools

Industry Keywords

Electrical EngineeringComputer EngineeringDigital ASICsSoCsPhysical DesignTiming ClosureDRCLVS

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Own SoC-level DFT implementation including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base-die designs
Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints
Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams
Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure
Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff
Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis

Requirements

What you’ll need

Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field
7+ years of proven experience in SoC development, DFT, or implementation for complex digital ASICs or SoCs
Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts
Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design
Proficiency with industry-standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation
Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation

Benefits

Comp & perks

Choice of medical, dental and vision plans
Income protection programs for illness or injury
Paid family leave
Robust paid time-off program
Paid holidays