Staff HBM Design Architect – DFT

Eightfold

HBM Design Architect defining and implementing DFT architectures for cutting-edge memory products. Collaborating across teams to ensure quality and performance in semiconductor designs.

Posted 5/14/2026full-timeRichardson • California, Texas • 🇺🇸 United StatesLead💰 $146,000 - $297,000 per yearWebsite

About the role

Key responsibilities & impact

Define and implement end-to-end DFT architectures for HBM base die and DRAM die
Develop DFT strategies for stacked-die, cube-level, and system-level test flows
Architect test access mechanisms supporting wafer probe through final test
Enable silicon observability for yield learning, debug, and failure analysis
Collaborate across design, verification, layout, test, and manufacturing teams

Requirements

What you’ll need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
Strong knowledge of scan, MBIST, JTAG, and boundary scan concepts
Experience with wafer probe and final test semiconductor flows
5+ years of experience in DRAM or ASIC DFT design or verification
Experience with HBM, DRAM, or advanced memory products
Knowledge of TSV-based 3D integration and stacked-die test challenges
Hands-on experience with at-speed test or advanced DFT techniques
Exposure to DFT security features or custom customer test interfaces

Benefits

Comp & perks

Choice of medical, dental and vision plans in all locations
Benefit programs to help protect income if unable to work due to illness or injury
Paid family leave
Robust paid time-off program
Paid holidays

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

DFT architecturesDFT strategiestest access mechanismssilicon observabilityscanMBISTJTAGboundary scanwafer probeat-speed test

Soft Skills

collaboration