HBM Memory Subsystem Architect – MTS/SMTS/DMTS

Eightfold

Memory Subsystem Architect focusing on innovative HBM product solutions for AI/ML workloads. Collaborating with cross-functional teams to drive architectural planning and performance analysis.

Posted 4/11/2026full-timeRichardson • California, Texas • 🇺🇸 United StatesSeniorLead💰 $177,000 - $387,000 per yearWebsite

About the role

Key responsibilities & impact

Develop innovative memory subsystem frameworks for HBM solutions supporting AI/ML workloads
Define Memory and RAS architecture requirements and drive architectural planning for next generation memory subsystems
Collaborate with internal and external partners to develop novel architectures and detailed IP requirements
Lead engagement with IP vendors, including evaluation and selection of interface and functional IP
Analyze benchmarks, workloads, and simulations to identify opportunities for performance, efficiency, and architectural innovation

Requirements

What you’ll need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
Minimum of 12 years of experience in memory subsystem architecture and design
Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM)
Experience with PHY design and understanding of signal integrity issues
Familiarity with industry-standard bus protocols such as AXI, AMBA, AHB, DFI, etc.

Benefits

Comp & perks

Choice of medical, dental and vision plans
Income protection programs
Paid family leave
Robust paid time-off program
Paid holidays

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

memory subsystem architecturememory controller designPHY designsignal integrityAI/ML workloadsbenchmarks analysisworkload simulationsinterface IP evaluationfunctional IP selectionRAS architecture

Soft Skills

collaborationleadershiparchitectural planning