Implement layout changes to resolve issues identified on current HBM designs on silicon and drive towards a timely and efficient tapeout.
Interact with teams like DE, PE, PI and TD to understand the challenges due to process limitations and propose layout solutions to alleviate the issues.
Be proactive in identifying and flagging design issues, performance problems, and opportunities to improve design performance and reduce power consumption.
Responsible for floor plans that optimize circuit placement, signal routing, and power delivery.
Deliver block-level (analog or mixed signal) layouts using advanced foundry process node if needed.
Contribute to the development of new HBM product opportunities by assisting with the overall planning and optimization of Memory, Logic, and Analog circuits layout.
Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products.
Mentor new hires as needed.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering or related field
8+ years (BS) or 6+ years (MS) of relevant experience
Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS
Strong grasp of analog layout fundamentals including matching, electro-migration, latch-up, coupling, crosstalk, IR-drop, and parasitics
Hands-on experience crafting analog and mixed-signal layouts (e.g., sense amplifiers, LDOs, PLLs)

Benefits

choice of medical, dental and vision plans
benefit programs to protect income if unable to work due to illness or injury
paid family leave
robust paid time-off program
paid holidays

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

analog layout fundamentalsmixed-signal layoutspower delivery optimizationsignal routingcircuit placementdebuggingroot cause analysisperformance improvementpower consumption reductiontapeout

Soft Skills

proactive problem solvingmentoring