Design Verification Engineer
EdgeCortix
full-time
Posted on:
Location Type: Office
Location: Kawasaki • 🇯🇵 Japan
Visit company websiteJob Level
Mid-LevelSenior
About the role
- Working closely with the design architecture team and contributing to IP, performance and SoC related verification.
- Playing a key role in development of verification infrastructure, which would involve VIPs, different memory models, monitors, etc.
- Writing configurable testbenches in SystemVerilog/UVM and testbench automation.
- Writing System verilog assertions and maintaining them.
- Writing functional coverage and overall functional and code coverage analysis.
- Working on ASIC power estimation and power-aware verification.
- Automating tool flows and creation of result reports.
Requirements
- 6-7 years of experience in functional verification of blocks/systems using SystemVerilog/UVM.
- Strong understanding of verification techniques including assertions, metric-driven and coverage-driven verification.
- Experience in developing full verification infrastructure from scratch.
- Experience with verification of systems which involve high-speed buses such as AXI4.
- Experience with gate level simulations and delay modeling.
- Experience with constraint random verification.
- Experience with writing functional coverage and overall code coverage analysis.
- Experience with coverage-driven verification methodology.
- Experience in writing and debugging System Verilog assertions.
- Strong experience in debugging RTL and testbenches.
Benefits
- Highly competitive salary and stock options
- Flex work time and ability to work fully remotely
- Support for obtaining a visa and relocation support (in case of non-remote)
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
SystemVerilogUVMfunctional verificationtestbench automationassertionsfunctional coveragecode coverage analysisASIC power estimationconstraint random verificationgate level simulations