Junior FPGA Engineer

Eagle Seven

Junior FPGA Engineer developing HDL solutions for high frequency trading systems. Collaborating with senior engineers on design, simulation, and validation of hardware modules.

Posted 7/23/2026full-timeChicago • Illinois • 🇺🇸 United StatesJunior💰 $150,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Proficient in SystemVerilog and Python for FPGA design and verification, with a strong focus on developing automated test scripts and comprehensive testbenches. Experienced in utilizing ModelSim for simulation and debugging, alongside a solid understanding of synchronous design and low-latency systems.

Highest-signal resume keywords

SystemVerilog ProficiencyModelSim ExperiencePython Automation SkillsFPGA Vendor Flows FamiliaritySynchronous Design Knowledge

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SystemVerilogPythonModelSimFPGA DesignTestbench DevelopmentData AnalysisSynchronous DesignState MachinesClock DomainsFIFO Structures

Tools & Technologies

ModelSimQuestaVivado SimulatorXilinx/AMD VivadoIntel/Altera Quartus

Industry Keywords

FPGATradingLow-Latency SystemsPCIeEthernetMemory InterfacesDDR

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Assisting in writing and maintaining clean, synthesizable SystemVerilog code for new features within our FPGA-based trading platform
Developing comprehensive testbenches using ModelSim to verify logic blocks and ensuring functional coverage before hardware deployment
Utilizing Python to create automated test scripts and data-processing tools that validate hardware outputs against expected trading model behavior
Supporting production deployments by capturing and analyzing various real-time data to identify design faults, edge cases, or timing issues
Maintaining clear design documentation and test results for all assigned modules

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science or other related disciplines
1-3 years of relevant experience; academic or internship experience with PCIe, Ethernet, or memory interfaces (DDR) preferred
Strong foundational knowledge of SystemVerilog (or Verilog) for design and verification
Hands-on experience with ModelSim (or similar tools like Questa, Vivado Simulator) for simulation, debugging, and waveform analysis
Proficiency in Python for automation, data analysis, and interacting with APIs
Solid understanding of synchronous design, state machines, clock domains, and FIFO structures
Familiarity with FPGA vendor flows (Xilinx/AMD Vivado or Intel/Altera Quartus) preferred
Demonstrated interest in finance, trading, and/or low-latency systems preferred

Benefits

Comp & perks

Medical PPO and HMO coverage through BlueCross BlueShield
Health Savings Account (with enrollment into a High Deductible Health Plan)
Dental coverage through Guardian
Vision coverage through VSP
401k Retirement Savings Plan with Employer Match
Company Paid Life Insurance
Company Paid Disability Insurance
Paid Time Off
Flexible Spending Account
Pre-tax Transit Benefits
Complimentary Lunch and Beverages