Analog/Mixed Signal Verilog Modeling Design Engineer

Broadcom

Engineer developing Digital-Mixed Signal models of analog IPs at Broadcom, collaborating with analog design and chip DV teams for verification.

Posted 7/7/2026full-timeIrvine • California • 🇺🇸 United StatesSeniorLeadWebsite

Tech Stack

Tools & technologies

DACPerlPython

About the role

Key responsibilities & impact

Responsible for developing Digital-Mixed Signal (DMS) models of analog IPs such as touch controller AFEs, wireless power charging, health sensing AFE and satellite AFEs using SystemVerilog language.
Interface with analog design team and chip DV team to develop and support analog/mixed signal models for chip verification.
Understand Verilog-AMS modeling language.

Requirements

What you’ll need

Bachelor's and 8+ years of related experience
Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package)
Familiar with analog circuits such as LDOs, TIAs, analog muxing, SARADC sample-and-hold (S/H), comparators, DAC voltage converter, buffering and amplification, etc.
Understand good coding of RTL of digital design (eg clock divider, decoder, FSM, etc) and testbench creation.
Fully familiar with how to run SV .vs. schematic verification for a given leaf SV model.
Familiar with Cadence linting & simulation tools (ncsim, xrun, vcs) and analog schematic editor.
Hands-on skills in scripting languages (TCL/Perl/Python)
Experience with using AI tools such as Cursor, chipAgents to generate analog SV models and testbench based on a given design spec.

Benefits

Comp & perks

Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

SystemVerilogVerilog-AMSRTL CodingAnalog Circuit DesignTestbench CreationSV vs. Schematic VerificationAI Tools for Model GenerationCadence LintingSimulation ToolsScripting (TCL/Perl/Python)