Senior Custom ASIC Engineering Lead

Broadcom

Senior engineer managing external customer ASIC programs for Broadcom in physical design, STA, DFT, and packaging. Leading cross-functional teams in ASIC product development.

Posted 6/20/2026full-timeSan Jose • California, Colorado • 🇺🇸 United StatesSenior💰 $143,800 - $230,000 per yearWebsite

ATS Keywords

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Hard Skills

physical designSTAEDA toolslogic simulationpackagingTCLshell scriptingVerilog RTL codingDFT methodslow power design

Soft Skills

team playerrisk assessmentcommunicationcustomer advisingmotivationcross-functional collaboration

Certifications & Qualifications

Bachelors degreeMasters degree

Industry Keywords

ASIC programstape-out quality standardsPPA tradeoffsSERDES communications protocolschip architecturemicroarchitecturefront-end logic design verificationDRClogic synthesismemory BIST

About the role

Key responsibilities & impact

Manage external customer ASIC programs from inception to finish, including RFQs, technology and IP collaterals, design, test, packaging, fabrication, bring-up and production
Advise customers on best practices in EDA, flows and design methodologies, and by organizing Q&A sessions with Broadcom technology experts
Proactively assess potential risks to the design quality and project schedule, then work with cross-functional teams to prepare and execute risk mitigation actions
Execute physical design flows to check that incoming customer tape-in netlists meet Broadcom’s stringent tape-out quality standards
Motivate and drive yourself to stay abreast of developments in Broadcom IPs, technology and end user applications
Participate in discussions about your chips with marketing, sales, legal and regulatory compliance teams
Be a consummate team player and assist other teams in need

Requirements

What you’ll need

Bachelors degree and 12+ years of related experience; or Masters degree and 10+ years of related experience
Multiple tape-outs in advanced technology nodes
Analyze PPA tradeoffs involved amongst various library components, and architectures
Knowledgeable in low power design and power management
Hands-on experience in physical design and STA, EDA tools, design flows for physical design, logic simulation, test, and packaging
Programming in TCL, shell and scripting languages
Exposure to SERDES communications protocols.
Logic design, chip architecture, microarchitecture, Verilog RTL coding
Front-end logic design verification, DRC, logic synthesis
Knowledge of DFT methods including scan, memory BIST and repair

Benefits

Comp & perks

Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave and vacation time
Paid Family Leave and other leaves of absence